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SUMMIT
MICROELECTRONICS, Inc.
S9318
Nonvolatile DACPOTTM Electronic Potentiometer With Up/Down Counter Interface
FEATURES * Digitally Controlled Electronic Potentiometer * 8-Bit Digital-to-Analog Converter (DAC) - Independent Reference Inputs - Differential Non-Linearity - 0.5LSB max - Integral Non-Linearity - 1LSB max * VOUT Value in E2PROM for Power-On Recall - Equivalent to 256-Step Potentiometer * Unity Gain Op Amp Drives up to 1mA * Simple Trimming Adjustment - Up/Down Counter Style Operation * Low Noise Operation * "Clickless" Transitions between DAC Steps * No Mechanical Wearout Problem - 1,000,000 Stores (typical) - 100 Year Data Retention * Operation from +2.7V to +5.5V Supply * Low Power, 1mW max at +5V
OVERVIEW The S9318 DACPOTTM trimmer is an 8-bit nonvolatile DAC designed to replace mechanical potentiometers. The S9318 includes a unity-gain amplifier to buffer the DAC output and enables VOUT to swing from rail to rail. The DACPOT trimmer operates over a supply voltage range of 2.7V to 5.5V. The S9318's simple up/down counter input provides an ideal interface for automatic test equipment to dither and monitor the VOUT voltage. This interface allows for quick and consistent calibration of even the most sophisticated systems. The S9318 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. The S9318 offers double the resolution of these devices and provides `clickless' transitions of VOUT.
FUNCTIONAL BLOCK DIAGRAM
VDD
8-bit E2 PROM
VH
-
UP/DN INC CS
Counter & Write Control
8-bit Data Register
AMP 8-bit DAC
+
VOUT
VL
GND
2016 ILL2.1
SUMMIT MICROELECTRONICS, Inc.
*
300 Orchard City Drive, Suite 131
*
Campbell, CA 95008
*
Telephone 408-378-6461
*
Fax 408-378-6586
*
www.summitmicro.com
(c) SUMMIT MICROELECTRONICS, Inc. 1999 2016-04 4/24/99
1
Characteristics subject to change without notice
S9318
PIN NAMES Symbol INC UP/DN VH GND VOUT VL CS VDD Description Increment Input, High to Low Edge Trigger Up/Down Input controlling relative VOUT movement V+ reference input Analog and Digital Ground Trimmed Voltage Output V- reference input Active low chip select input Supply Voltage (2.7V to 5.5V)
2016 ILL1.1
PINOUT
INC UP/DN VH GND
1 2 3 4
8 7 6 5
VDD CS VL VOUT
Analog Section The S9318 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts an 8-bit value into equivalent analog output voltages in proportion to the applied reference voltage. Reference Inputs The voltage differential between the VL and VH inputs sets the full-scale output voltage range. VL must be equal to or greater than ground (i.e. a positive voltage). VH must be greater than VL and less than or equal to VDD. See table on page 3 for guaranteed operating limits. Output Buffer Amplifier The voltage output is a precision unity-gain follower that can slew up to 1V/s. Digital Interface The interface is designed to emulate a simple up/down counter, but instead of a parallel count output, a ratiometric voltage output is provided.
Chip Select (CS is an active low input. Whenever CS is CS) CS high the S9318 is in standby mode and consumes the least power. This mode is equivalent to a potentiometer that is adjusted to the required setting. When CS is low the S9318 will recognize transitions on the INC input and will move the VOUT either toward the VH reference or toward the VL reference depending upon the state of the UP/DN input. The host may exit an adjustment routine in two ways: deselecting the S9318 while INC is low will not perform a store operation (a subsequent power cycle will recall the original data); deselecting the S9318 while INC is high will store the current VOUT setting into nonvolatile memory. Increment (INC is an edge triggered input. Whenever INC) INC CS is low and a high to low transition occurs on the INC input, the VOUT voltage will either move toward VH or VL depending upon the state of the UP/DN input. UP/Down (UP/DN is an input that will determine the VOUT DN) DN movement relative to VH and VL. When CS is low, UP/DN is high and there is a high to low transition on INC, the VOUT voltage will move (1/256th x VH-VL) toward VH. When CS and UP/DN are low, and there is a high to low transition on INC, the VOUT will move (1/256th x VH-VL) toward VL.
2016-04 4/24/99
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S9318
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias Storage Temperature Voltage on pins with reference to GND: Analog Inputs Digital Inputs Analog Outputs Digital Outputs Lead Solder Temperature (10 secs) -55C to +125C -65C to +150C -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V 300C *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RECOMMENDED OPERATING CONDITIONS Condition Temperature VDD
Min -40C +2.7V
Max +85C +5.5V
2016 PGM T1.1
DAC DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40C to +85C, unless specified otherwise
Symbol Parameter Integral Non-Linearity Differential Non-Linearity VrefH Input Voltage VrefL Input Voltage VrefH to VrefL Resistance Temperature Coefficient of RIN Full-Scale Gain Error VrefH to VrefL DATA = FF Conditions ILOAD = 100A, ILOAD = 100A, Guaranteed but not tested Min. VrefL Gnd 0 -200 VDD = +5V VDD = +3V 10 20 90 0.08 300 1 Typ. 0.5 0.1 38K 600 Max. 1 0.5 VDD VrefH 1 20 50 +1000 Units LSB LSB V V ppm/C LSB mV V/C A LSB/V nV/ % kHz
2016 PGM T3.4
Accuracy
INL DNL
References VH
VL RIN TCRIN
Analog Output
GEFS VOUTZS TCVOUT
Zero-Scale Output Voltage DATA = 00 VOUT Temperature Coefficient Amplifier Output Load Current Amplifier Output Resistance IL = 100A Power Supply Rejection Amplifier Output Noise Total Harmonic Distortion Bandwidth - 3dB ILOAD = 10A f = 1KHz, VDD = +5V VIN = 1V rms, f = 1KHz VIN = 100mV rms VDD = +5, ILOAD = 50A, VrefH = +5V, VrefL = 0V Guaranteed but not tested
IL ROUT PSRR eN THD BW
HZ
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S9318
RELIABILITY CHARACTERISTICS Symbol VZAP ILTH TDR NEND Parameter ESD Susceptibility Latch-Up Data Retention Endurance Min 2000 100 100 1,000,000 Max Unit V mA Years Stores Test Method MS-883, TM 3015 JEDEC Standard 17 MS-883, TM 1008 MS-883, TM 1033
2016 PGM T2.0
DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, Unless otherwise specified Symbol IDD ISB IIH IIL VIH VIL
Notes: 1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference resistor chain. 2. CS, UP/DN and INC have internal pull-up resistors of approximately 200k. When the input is pulled to ground the resulting output current will be VDD/200k.
Parameter Supply Current during store, note 1 Supply Standby Current Input Leakage Current Input Leakage Current, note 2 High Level Input Voltage Low Level Input Voltage
Conditions CS = VIL CS = VIH VIN = VDD VIN = 0V
Min
Max 1.2 200 10 -25
Units mA A A A V V
2016 PGM T4.3
2 0
VDD 0.8
2016-04 4/24/99
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S9318
OPERATIONAL TRUTH TABLE INC HITOLO HITOLO H L VDD CS L L LOTOHI LOTOHI VDD UP/DN DN H L X X VDD Operation VOUT toward VH VOUT toward VL Store Setting Maintain Setting, NO Store Standby
2016 PGM T5.1
AC TIMING CHARACTERISTICS VDD = +4.5V to +5.5V Symbol tCLIL tIHDC tDCIL tIL tIH tIHCH tWP tILVOUT Parameter CS to INC Setup INC High to UP/DN Change UP/DN to INC Setup INC Low Period INC High Period INC Inactive to CS Inactive Write Cycle Time INC to VOUT Delay Min 100 100 100 200 200 100 5 5 Max Units ns ns ns ns ns ns ms s
2016 PGM T6.1
CS tCLIL tIL tIH tIHCH tWP
INC tIHDC UP/DN tIHDHLD
tILVOUT VOUT
2016 ILL3.1
AC TIMING DIAGRAM
2016-04 4/24/99
5
S9318
8 Pin SOIC (Type S) Package JEDEC (150 mil body width)
.050 (1.27) TYP. .050 (1.270) TYP. 8 Places
.157 (4.00) .150 (3.80)
.275 (6.99) TYP.
1 .196 (5.00) .189 (4.80)
.030 (.762) TYP. 8 Places
FOOTPRINT
.061 (1.75) .053 (1.35) .020 (.50) x45 .010 (.25)
.0192 (.49) .0138 (.35)
.0098 (.25) .004 (.127) .05 (1.27) TYP.
.035 (.90) .016 (.40)
.244 (6.20) .228 (5.80)
8pn JEDEC SOIC ILL.2
ORDERING INFORMATION
S9318
S
Base Part Number
Package S = 8 Pin SOIC
2016 ILL4.1
NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
(c) Copyright 1999 SUMMIT Microelectronics, Inc.
2016-04 4/24/99
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